1. Field of the Invention
This invention relates generally to integrated circuit design and, in particular, to placing functional elements within an integrated circuit floorplan.
2. Description of the Related Art
For the design of digital circuits on the scale of VLSI (Very Large Scale Integration) technology, designers often employ computer-aided techniques. Standard languages known as Hardware Description Languages (HDLs) have been developed to describe digital circuits to aid in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general-purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL), or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
In designing circuits using HDL compilers, designers first describe circuit elements in HDL source code and then compile the source code to produce synthesized RTL netlists. The RTL netlists correspond to schematic representations of the circuit elements. The circuits containing the synthesized circuit elements are often optimized to improve timing relationships and eliminate unnecessary or redundant logic elements. Such optimization typically involves substituting different gate types or combining and eliminating gates in the circuit, and often results in re-ordering the hierarchies and relationships between the original RTL objects and the underlying source code that produced the RTL objects.
One operation, which is often desirable in this process, is to plan the layout of a particular integrated circuit, to control timing problems and to manage interconnections between regions of an integrated circuit. This is sometimes referred to as “floorplanning.” A typical floorplanning operation divides the circuit area of an integrated circuit into regions, sometimes called “blocks,” and then assigns logic to reside in a block. This operation has two effects: the estimation error for the location of the logic is reduced from the size of the integrated circuit to the size of the block (which tends to reduce errors in timing estimates), and the placement and the routing typically runs faster because as it has been reduced from one very large problem into a series of simpler problems.
Once the placement and routing operations have been applied to the floorplan, there may be adjustments that are necessary to accommodate timing constraints not satisfied through the placement and routing design software. These designs, while being close to being complete, may require hand placement for fine-tuning. However, in order to visibly see and have access to the functional element in the floorplan, the floorplan must be greatly expanded. As a result, only a small fraction of the floorplan will be viewed on the display monitor. To move a functional element from one end of the floorplan to another end, the functional element will have to be dragged while scrolling from one end of the floorplan to the other. The scrolling is a slow process. Additionally, moving a large number of functional elements becomes even more difficult because of the repeated slow scrolling.
As a result, there is a need to solve the problems of the prior art to more efficiently fine tune a floorplan design of an integrated circuit.